CODESYS runtime latency test and scan jitter surprises

In hard-tech automation, small timing deviations can trigger costly instability. This article explores a real CODESYS runtime latency test, unexpected scan jitter behavior, and what those results mean for engineers evaluating real time operating system RTOS benchmark data, OPC UA server response time, EtherCAT cycle time benchmark, and PLC vs PAC performance comparison in demanding industrial control environments.

For R&D engineers, machine builders, plant operators, procurement teams, and technical decision-makers, the challenge is rarely the headline cycle time printed on a vendor brochure. The real question is how a controller behaves after 8 hours, 24 hours, or 30 days of mixed communication, fieldbus traffic, HMI updates, logging, and interrupt load.

That is where latency and scan jitter become commercially important. A nominal 1 ms task that occasionally slips to 3 ms may still look acceptable in a demo, but in synchronized motion, deterministic I/O, or closed-loop edge control, that deviation can be the difference between stable throughput and recurring troubleshooting costs.

At TechStat Vanguard, the focus is not on marketing adjectives but on measurable engineering behavior. The purpose of this analysis is to explain what runtime latency actually reveals, why scan jitter often surprises teams evaluating CODESYS platforms, and how to interpret benchmark data before choosing hardware, RTOS architecture, or a PLC vs PAC control strategy.

Why CODESYS runtime latency matters beyond the headline scan time

CODESYS is widely used because it offers portability across industrial hardware, standardized IEC 61131-3 development, and practical deployment in embedded control, gateways, soft PLCs, and machine controllers. However, portability does not guarantee deterministic timing. Runtime latency depends on the operating system layer, CPU isolation, interrupt behavior, fieldbus driver quality, and the number of competing software services.

In many projects, engineers begin by testing a cyclic task at 1 ms, 2 ms, or 4 ms. The initial result may appear stable for 10 to 15 minutes. Problems often surface only after OPC UA polling, historian writes, HMI rendering, and EtherCAT traffic are added together. That is why a proper latency test must simulate realistic industrial load rather than a single idle loop.

Scan jitter is the variation around the expected execution interval. If a task is configured for 1.000 ms but actually arrives at 0.98 ms, 1.04 ms, 1.30 ms, and occasionally 2.10 ms, the average may still look reasonable while the worst-case behavior becomes unacceptable. For procurement teams, this distinction is critical because average values rarely capture downtime risk.

What engineers should measure in a latency test

A meaningful benchmark should capture at least 5 timing dimensions: configured task interval, average execution time, average latency, peak latency, and jitter spread over a fixed duration such as 2 hours, 8 hours, or 24 hours. Without a long enough sample window, rare spikes caused by driver contention or network interrupts may never be observed.

• Configured cycle time, such as 1 ms, 2 ms, 5 ms, or 10 ms
• Average task latency over a sustained run, ideally above 2 hours
• Peak or worst-case latency, not just mean value
• Jitter distribution under idle and loaded states
• Communication impact from OPC UA, fieldbus, logging, and HMI traffic

The table below separates metrics that are often confused during vendor evaluation. This matters because two systems can both claim a 1 ms cycle, yet one may be suitable for deterministic machine control while the other is only acceptable for general automation sequencing.

The practical takeaway is simple: a clean average does not prove real-time reliability. Teams comparing CODESYS targets should request test logs that show percentile behavior and worst-case events, especially if the intended deployment includes EtherCAT synchronization, edge analytics, or OPC UA data exposure at the same time.

What the latency test revealed and why the jitter was surprising

In a representative test scenario, a CODESYS runtime was configured with a 1 ms cyclic task and monitored across multiple operating conditions: idle state, active OPC UA reads, HMI refresh, event logging, and EtherCAT process data exchange. During the first phase, average latency remained low, typically below 100 µs. The surprise appeared when mixed workload was introduced.

Under moderate communication load, the average value still looked acceptable, but jitter widened sharply. Instead of staying within a narrow band such as ±25 µs to ±50 µs, the task occasionally drifted into several hundred microseconds, with rare spikes above 1 ms. For general sequencing this may be tolerable, but for tightly synchronized control it changes the risk profile immediately.

This is the kind of result that surprises teams who only inspect “typical” scan time. A machine can pass a factory demo while still carrying a hidden timing weakness. Once deployed in the field, the added noise of production networks, larger tag sets, or more frequent OPC UA subscriptions can expose that weakness in a way that is expensive to diagnose.

Common sources of unexpected scan jitter

Unexpected jitter rarely comes from one cause alone. In most embedded or industrial PC deployments, it is the combined effect of scheduler behavior, driver stack overhead, and communication bursts. Even with a capable multicore CPU, poor core affinity or non-deterministic background services can disrupt timing.

Typical contributors engineers should